"make" makes making easier

+4 M .A.K · May 31, 2014
make is a gcc common command to produce a target file using recipes and dependencies.
recipes and dependencies make rules that tell "make" how to produce the target file.
Here is an exp:

                       Imagine you have a newstuff.c file and want it to be compiled and generate newstuff.o file(object file)
                       so newstuff.c will be your dependency and so what's the recipe?
                             gcc -c newstuff.c

make any sense? if you tell make about newstuff.c and recipe it will do the rest for you.
going even further after making newstuff.o file you need to link it to create executable(launch).
so now launch is our target newstuff.o our dependency and recipe: 
                                                                                gcc newstuff.o -o launch
How to tell make about all this stuff?
create a new file named "makefile" at the same directory as newstuff.c (file you want to be compiled and linked)
and paste this code there:

launch: newstuff.o
gcc newstuff.o -o launch 
newstuff.o: newstuff.c
gcc -c newstuff.c

now open a terminal cd to proper directory and just type "make" and it's all you need to create "launch" executable.

syntax guide:

target: dependency anotherdependency onemoredependency 

Things to consider: 

    1-Those  indented lines must (must must ....) be  indented  using only and only one tab!(can't use space or whatever!).
    2-you can also write makefile this way:

newstuff.o: newstuff.c
gcc -c newstuff.c
launch: newstuff.o
gcc newstuff.o -o launch 

But then you most type "make launch" to run make properly.
 3- you don't have to use "make" only for programming stuff whatever that has a target,dependencies and recipe will do the job(like making zip files)


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+2 Jayanth Varma B · June 13, 2014
Not completely understood but enlightened me enough to try out 'make' and learn more about it :)
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